The invention relates to the field of clock selection, and in particular to glitch-free clock selection.
Digital electronic systems often rely upon a clock signal to synchronize and control the operation of the various circuit elements (e.g., gates, flip-flops, latches, etc.). In many present day digital electronic systems, such as microprocessor-based devices, there exist multiple clock sources and a concomitant need to switch between them.
When switching between clocks, it is preferable to avoid glitches and intermediate clock behavior on the clock output of the selection circuitry. FIGS. 1a and 1b help illustrate the occurrence of a glitch when switching between clock sources. FIG. 1a shows a typical circuit for switching between clock sources. As shown in FIG. 1a, two clock signals, CLOCK_1 and CLOCK_2, are provided as inputs to a switching circuit 100, such as a multiplexor. Multiplexor 100 also receives a Select signal, which switches the output signal, CLOCK_OUT, between the input signals CLOCK_1 and CLOCK_2. For instance, when the Select signal is high, CLOCK_1 is output on CLOCK_OUT and when the Select signal is low, CLOCK_2 is output on CLOCK_OUT. FIG. 1b illustrates a timing relationship between the Select signal, CLOCK_1 and CLOCK_2 that results in a glitch on CLOCK_OUT. As shown, the Select signal is initially high, resulting in CLOCK_1 being output on CLOCK_OUT. The Select signal then goes low while CLOCK_1 is high and CLOCK_2 is low. This results in a shortened pulse 102, i.e. a glitch, output on CLOCK_OUT.
Generally, a glitch signal causes errors during execution of a microprocessor and other components because a glitch may erratically clock subsequent flip-flops, latches, etc. Therefore, there is a need for a switching circuit that enables switching of the clock source, dynamically and cleanly, without any perturbation on the logic driven by the clock.
In one aspect of the present invention, a clock selection circuit for switching between a plurality of possible clocks is provided. A switch made from an existing clock to a new frequency clock is made in synchronization with both the existing and the new frequency clock. The clock selection circuit comprises a first clock input to receive the existing clock as input and a new frequency clock input to receive the new frequency clock. The circuit also comprises first synchronization logic associated with the first clock to enable/disable output of the existing clock and second synchronization logic associated with the new frequency clock to enable/disable output of the new frequency clock. The first synchronization and second synchronization logic cooperates to disable output of the existing clock synchronously to the existing clock and to enable output of the new frequency clock synchronously to the new frequency clock.
In another aspect of the present invention, a clock selection circuit for outputting an input clock signal selected from among a plurality of input clocks is provided. The circuit comprises enable logic responsive to a clock select input to generate, for each input clock, an associated select signal. Each select signal is indicative of whether or not its associated input clock is selected to be output. For each select signal, there is synchronization logic responsive to the select signal to generate an enable signal synchronously to the select signal""s associated input clock. The enable signal is indicative of whether or not the select signal""s associated clock is to be output. Output logic is responsive to the enable signals to output the selected input clock.
In another aspect of the present invention, a clock selection circuit for switching from a first clock signal coupled to an output to a second clock signal coupled to the output is provided. The circuit comprises enable logic responsive to a clock select signal to generate a first select signal that indicates the first clock is to be decoupled from the output and a second select signal that indicates the second clock signal is to be coupled to the output. First synchronization logic is responsive to the first select signal to generate a first enable signal synchronously to the first clock. The first enable signal indicates that the first clock is to be decoupled from the output. Second synchronization logic is responsive to the second select signal to generate a second enable signal synchronously to the second clock. The second enable signal indicates the second clock signal is to be coupled to the output. The first enable signal is generated before the second enable signal is generated. Output logic is responsive to the first enable signal to decouple the first clock signal from the output and responsive to the second enable signal to couple the second clock signal to the output.
In another aspect of the present invention, a method of switching from a first clock signal coupled to an output of a clock selection circuit to a second clock signal coupled to the output of the clock selection circuit is provided. An indication to switch from outputting the first clock signal to the second clock signal is received. The first clock is then removed from output synchronously to the first clock. The second clock signal is then coupled to the output synchronously to the second clock signal.